Senior SoC STA Engineer

Responsibilities

• Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, process corners, voltage, and temperature conditions
• Develop, maintain, and validate sign-off-quality SDC constraints for clocks, resets, high-speed I/O interfaces, DFT, and configuration logic
• Drive timing closure at both block and full-chip levels through critical path analysis and ECO implementation
• Perform advanced multi-mode multi-corner (MMMC) timing analysis including clock-domain crossing and OCV/AOCV/POCV methodologies
• Lead signal integrity and crosstalk analysis and drive mitigation strategies
• Conduct pre- and post-silicon timing correlation and drive tape-out closure activities
• Build and maintain STA automation and reporting flows using Python and Tcl
• Mentor junior engineers and contribute to technical documentation and sign-off methodologies

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline
• 10+ years of hands-on experience in chip-level STA ownership and full timing sign-off
• Experience with multiple successful tape-outs at 22nm technology nodes or below
• Deep expertise with industry-standard STA tools such as Cadence Tempus
• Strong understanding of MMMC analysis, OCV/AOCV/POCV, signal integrity, and crosstalk
• Proven experience developing complex hierarchical SDC constraints for large SoCs
• Solid understanding of Logic Synthesis and Physical Design methodologies
• Strong scripting and automation skills using Python and/or Tcl
• Familiarity with DFT timing analysis including scan, MBIST, and JTAG interfaces

About the Company

InnoPhase IoT is a technology company that values working smart, celebrating successes, and providing an environment where employees can learn and experience different aspects of work in a high-growth setting.