Senior SoC Design Verification Engineer

Responsibilities

• Perform pre-silicon system verification for SoC, FPGA, and full chip designs
• Create test cases and test benches using UVM methodology
• Define verification strategies, methodologies, and test plans to ensure effective full-chip and system functional verification
• Coordinate cross-functional efforts with Design, Software, and Architecture teams to achieve full coverage verification plans
• Use system full applications to verify performance and identify potential shortfalls

Requirements

• 10+ years of experience with complex ASIC design or verification
• Proficiency in SystemVerilog
• Extensive experience with UVM verification methodology and formal verification methods
• Experience with Design for Debug architectures, including JTAG, high-speed USB, and PCIe-based debug
• Knowledge of ARM or RISC Debug Architectures
• Proficiency in Linux/Unix scripting and Perl or Python
• Strong communication skills and ability to work with geographically distributed teams

Preferred Qualifications

• Experience with Emulation
• Prior working experience with UltraSoC or Tessent Embedded Analytics Debug Architecture

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs, and IPUs.