Senior Semiconductor Reliability Engineer

About the Company

At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

Responsibilities

• Define reliability requirements for advanced silicon nodes and package platforms
• Perform pre-silicon reliability risk assessments across silicon, interconnect, and package technologies
• Evaluate reliability mechanisms including EM, TDDB, BTI, HCI, BEOL, and silicon-package interaction
• Support design reviews, guard-banding, and reliability sign-off activities
• Develop and execute qualification plans aligned with JEDEC and customer requirements
• Lead HTOL, thermal cycling, thermal shock, and reflow qualification testing
• Drive correlation between pre-silicon modelling and post-silicon qualification results
• Lead root-cause analysis of silicon and package-related failures
• Utilize X-ray and CSAM analysis to diagnose package defects
• Work with foundries, OSATs, and reliability labs to resolve issues
• Author qualification reports, risk assessments, and reliability documentation
• Mentor engineers and contribute to reliability best practices

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or Mechanical Engineering
• 8+ years of semiconductor reliability engineering experience
• Strong understanding of silicon reliability mechanisms (EM, TDDB, BTI, HCI)
• Experience with BEOL, interconnect, and advanced package reliability
• Hands-on experience with HTOL, thermal cycling, thermal shock, and reflow testing
• Experience using X-ray and CSAM for package failure analysis
• Familiarity with JEDEC reliability standards

Preferred Qualifications

• Experience with leading-edge nodes, AI accelerators, or high-performance SoCs
• Knowledge of HBM, chiplets, TSVs, micro-bumps, and 2.5D/3D integration
• Experience with wafer-level reliability or system-level stress testing
• Experience working with foundries and OSAT partners
• Technical leadership or mentoring experience