Senior RTL Engineer, Interconnect Design at OpenAI - ScoutJobs - The AI-curated global job board
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OpenAI
Posted 17 days ago

Senior RTL Engineer, Interconnect Design

OpenAISenior RTL Engineer, Interconnect Design

Perks & benefits

VisaMedical InsuranceHealth InsuranceHousing AllowanceMobile AllowancePaid LeaveRelocation AllowanceTransportation

Requirements

Extensive SoC interconnect or NoC design experience, Expertise in Verilog/SystemVerilog, Knowledge of AXI, APB, CXL, PCIe, or Ethernet, Experience with RTL signoff flows (lint, CDC, synthesis), Experience with large-scale systems (RDMA/RoCE)

Skills

VerilogSystemVerilogSOCNOCAXIPCIe

About the role

Responsibilities

  • Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including NoC fabrics, switches, routers, and protocol adapters.
  • Drive the implementation of off-chip protocol bridges and interfaces for custom AI accelerator platforms.
  • Collaborate with architecture and performance teams to analyze traffic patterns and optimize interconnect behavior.
  • Partner with physical design teams to ensure structures meet target frequency, power, and area constraints.
  • Provide technical leadership through design reviews, documentation, and mentoring of junior engineers.
  • Manage third-party engagements to develop novel networking and interface protocols and silicon IP.

Requirements

  • Extensive industry experience designing complex SoC interconnects, NoC, or coherent fabrics.
  • Deep expertise in Verilog/SystemVerilog and developing production-quality, parameterized RTL.
  • Strong understanding of interconnect concepts such as topology, arbitration, flow control, and congestion management.
  • Proficiency with protocols such as AXI, APB, CXL, PCIe, or Ethernet.
  • Experience with RTL signoff flows, including lint, CDC/RDC, synthesis, and static timing analysis.
  • Experience designing subsystems for large-scale systems using RDMA/RoCE or HPC-style interconnects.

Preferred Qualifications

  • Experience designing interconnects for AI accelerators, GPUs, or high-performance computing systems.
  • Knowledge of memory consistency, virtualization, isolation, or security requirements within complex SoCs.
  • Experience with NoC performance modeling, traffic simulation, or FPGA prototyping.
  • Proven track record leading RTL delivery for first-generation silicon programs.

Benefits

  • Competitive salary range of $225K – $445K plus generous equity and performance bonuses.
  • Comprehensive medical, dental, and vision insurance for you and your family.
  • 401(k) retirement plan with employer match.
  • Flexible PTO and significant paid parental leave.
  • Daily meals in the office and mental health/wellness support.
  • Annual learning and development stipend.

About the Company

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. Our Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads, building next-generation AI-native infrastructure to support large-scale training and inference systems.

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Senior RTL Engineer, Interconnect Design

OpenAI · San Francisco

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