Senior Principal Verification Engineer, Digital IP

Responsibilities

• Lead the pre-silicon verification of IP modules and IP subsystems.
• Define and write comprehensive IP verification plans based on industry standards, product requirements, and architecture specifications.
• Interface with HW, FW, SW, architecture, and system engineering teams to understand IP functionality and applications.
• Architect, develop, debug, and execute UVM-based verification environments for RTL simulation.
• Develop test cases, create stimulus and assertions, and run simulations across various platforms including RTL, gate level, FPGA, and Emulation.
• Execute regressions and perform detailed analysis of code and functional coverage.

Requirements

• Degree in Electrical Engineering or Computer Science.
• 12+ years of experience in IP or Sub-System Verification.
• Proven expertise in testbench design and development using UVM methodology for IP, Subsystems, and SoCs.
• Advanced proficiency in Verilog, System Verilog, C/C++, and Shell scripting.
• Strong knowledge of Metric Driven Verification (MDV) concepts, including functional and code coverage.
• High proficiency in directed and constrained random methodologies.
• Experience with formal verification methodologies and assertions.
• Experience debugging designs in both pre-silicon (simulation) and post-silicon (on the bench) environments.
• Excellent written and verbal communication skills.

Preferred Qualifications

• Prior experience serving as a technical lead or Design Verification (DV) manager.
• Proficiency in scripting languages such as Perl, TCL, or Python.

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a global leader in secure connectivity solutions for embedded applications, NXP provides industry-leading solutions across the automotive, industrial & IoT, mobile, and communication infrastructure markets.