Senior Principal Physical Design Engineer

Responsibilities

• Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII, including floor planning, power planning, place and route, and clock tree synthesis.
• Drive and optimize design methodologies, flows, and scripts to improve efficiency and design quality.
• Perform critical path analysis and provide innovative solutions to meet aggressive frequency and power targets.
• Collaborate with design, architecture, and verification teams to resolve complex technical issues.
• Mentor junior and mid-level engineers, providing technical guidance and fostering professional growth.
• Evaluate and integrate new EDA tools and technologies to enhance physical design capabilities.
• Implement low-power design techniques such as clock gating, power gating, and multi-voltage design.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 15+ years of extensive experience in ASIC physical design with a track record of successful tape-outs on advanced process nodes.
• Deep expertise in industry-standard EDA tools such as Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, or Ansys RedHawk.
• Proficiency in scripting languages including Tcl, Perl, or Python for automation and flow development.
• Strong understanding of static timing analysis (STA) concepts, constraints, and methodologies.
• Hands-on experience with low-power design techniques and methodologies.
• Solid understanding of semiconductor physics, process technology, and DFM principles.

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.