Senior Principal DFT Designer - MCU

Responsibilities

• Lead and execute the full DFT design flow, including specification definition, architectural design, RTL coding, synthesis, and static timing analysis.
• Develop and integrate scan insertion, test compression, ATPG patterns, and memory BIST strategies.
• Collaborate with RTL, physical design, verification, and product teams to ensure timing closure and robust testability.
• Implement innovative DFT architectures to meet performance, power, area, and quality targets.
• Optimize test coverage, pattern count, and test time while performing comprehensive DFT verification at RTL and gate level.
• Work with ATE teams for test program development and participate in silicon debug and post-silicon validation.
• Mentor junior engineers and provide technical guidance to improve DFT design processes.

Requirements

• Bachelor or master degree in microelectronics, electronic engineering, or a related field.
• Strong expertise in DFT methodologies including Scan, MBIST, LBIST, and JTAG.
• Hands-on experience with industry-standard ATPG tools.
• Proficiency in UPF/CPF-based low-power DFT.
• Knowledge of fault models such as stuck-at, transition, and path delay.
• Experience in silicon debug and ATE bring-up.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Good English communication capabilities and strong teamwork skills.

About the Company

NXP enables a smarter, safer, and more sustainable world through innovation. As a global leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.