Senior Physical Design Engineer

Responsibilities

• Execute block-level physical design from synthesized netlist to GDSII, including floorplanning, power grid design, placement, CTS, and routing
• Drive timing convergence across MCMM scenarios in collaboration with STA teams
• Ensure design closure for setup/hold timing, DRC/LVS clean signoff, and IR drop/EM compliance
• Debug and resolve congestion, SI/crosstalk problems, and functional/physical ECOs
• Collaborate cross-functionally with RTL, DFT, and packaging teams to improve QoR
• Contribute to methodology improvements and automation through scripting

Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or Microelectronics
• 3–5 years of experience in ASIC Physical Design
• Strong understanding of physical design flow (FP to P&R) and Static Timing Analysis fundamentals
• Hands-on experience with Cadence (Innovus/Genus) or Synopsys (ICC2/Fusion Compiler, PrimeTime)
• Proficiency in scripting languages such as Tcl, Python, or Shell

Preferred Qualifications

• Experience working with advanced technology nodes (16nm and below)
• Knowledge of low-power design flows (UPF/CPF) and multi-voltage/multi-domain designs
• Experience with high-speed interfaces such as PCIe, DDR, or Automotive SerDes
• Familiarity with physical verification tools like Calibre or Pegasus

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.