Senior Physical Design Engineer

Responsibilities

• Own end-to-end physical design flow including floorplanning, placement, CTS, routing, STA, and physical verification
• Perform timing closure for high-speed PCIe Gen 4/5/6 interfaces across PVT corners
• Drive power integrity analysis including IR drop and electromigration (EM)
• Achieve physical verification closure including DRC, LVS, and ERC signoff using Calibre
• Work with RTL and synthesis teams to provide feedback on logic restructuring
• Contribute to internal PD methodology and flow automation using Perl and Tcl
• Support tapeout activities including final GDS merge and signoff checks

Requirements

• B.S. / M.S. in Electrical Engineering, Computer Engineering, or related field
• 5+ years of hands-on physical design experience in advanced TSMC process nodes (N6 and below preferred)
• Strong knowledge of PCIe protocol and high-speed interface physical design constraints
• Strong hands-on experience with CTS for high-speed designs
• Proficiency with Cadence Innovus, Synopsys Primetime, or Tweaker
• Experience in resolving chip level DRC, LVS, and EMIR issues
• Proven tape out experience

Preferred Qualifications

• Experience in multi-die packaging (WoW, 2.5D / 3D)
• Experience with Thermal, IR, or EM signoff
• Experience with signal integrity or DFT-aware physical design
• Proficiency in Python, Perl, Tcl, or Make scripting

About the Company

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud, designing industry-leading ASIC chips and managing complex computing processes across the value chain.