Senior Mixed-Signal Verification Engineer

Responsibilities

• Develop high-level behavioral models for analog and mixed-signal IP including ADCs, DACs, PLLs, and LDOs
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog
• Develop regression infrastructure and mixed-signal testbenches for digital and analog co-simulation
• Integrate AMS models into UVM-based digital verification environments
• Define and build mixed-signal verification methodology for top-level SoC and subsystem verification
• Support architectural exploration through early-phase modeling and system-level simulations
• Collaborate with analog/RF designers to capture real-world analog behaviors
• Provide modeling and verification insights during architectural reviews and silicon bring-up
• Act as technical leader and subject-matter expert

Requirements

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in analog/mixed-signal modeling and/or AMS verification
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers)
• Experience with mixed-signal co-simulation environments such as Cadence AMS Designer or Synopsys VCS AMS

Preferred Qualifications

• Experience building AMS verification methodologies from scratch
• Familiarity with UVM-based verification and digital design flows
• Knowledge of signal processing theory, RF system modeling, or communication systems
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS
• Experience working in cross-functional, geographically distributed teams

About the Company

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by leading investors, K2 is mass-producing high-power satellite platforms for missions ranging from LEO to deep space.