Senior Manager, Embedded Memory

Responsibilities

• Lead architecture, circuit design, and physical implementation of memory compilers (SRAM, ROM, register files, DPRAM)
• Define bitcell selection, peripheral architecture, redundancy, and repair strategies to hit PPA targets
• Own the technical roadmap for the memory portfolio across new nodes and feature enhancements
• Lead, mentor, and grow a team of memory design engineers
• Serve as the senior technical lead in presales engagements and customer technical workshops
• Perform PPA analysis and maintain competitive benchmarks against foundry and third-party IP
• Act as the primary technical point of contact for strategic customers through integration and silicon validation

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field
• 10+ years of embedded memory design experience with production tapeouts
• Deep expertise in bitcell-level circuit design and memory peripherals
• Hands-on experience with FinFET and/or advanced sub-7nm nodes
• Proficiency in SPICE simulation, Monte Carlo analysis, and Vmin/yield modeling
• Experience with DFT/scan tools, power integrity signoff, and layout verification
• Proven team leadership experience managing 6+ engineers
• Experience in customer-facing technical roles such as presales or PPA negotiation
• Proficiency with Python, TCL, Perl, and Linux-based environments

Preferred Qualifications

• Experience leading memory compiler programs at an IP vendor or foundry
• Background in low-power memory design for mobile, IoT, automotive, or AI/ML applications
• Experience with multi-port memory architectures and specialty memories like TCAM