Senior Layout Engineer

Responsibilities

• Design and develop high-quality IP layouts used in DRAM chips
• Perform layout verification including LVS, DRC, and EM, ensuring quality checks and proper documentation
• Ensure on-time delivery of block-level layouts meeting quality standards
• Guide and lead team members in the execution of sub-block level layouts and perform work reviews
• Contribute to effective project management and collaborate with global engineering teams in the US, India, and Japan

Requirements

• Experience performing physical layout using Cadence Virtuoso or similar tools
• Familiarity with DRC, LVS, physical verification, and reliability checks
• Strong understanding of circuit design principles to create high-performance, area-optimal layouts
• Hands-on experience with critical analog layout design for blocks such as PLL, ADC, DAC, LDO, Bandgap, and Charge Pumps
• Deep understanding of analog layout fundamentals including matching, electro-migration, latch-up, crosstalk, and IR-drop

Preferred Qualifications

• Experience with DRAM, memory circuits, or large-scale hierarchical designs
• Background in parasitic extraction flows and post-layout optimization
• Hands-on experience with partial custom layout for devices and small analog blocks
• Strong communication skills for supporting global engineering collaboration

Benefits

• Choice of medical, dental, and vision plans
• Income protection programs for illness or injury
• Paid family leave
• Robust paid time-off program and paid holidays

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.