Senior IC Packaging Engineer

Responsibilities

• Serve as technical authority for IC and SiP packaging across multiple products and programs
• Own package architecture and technology roadmap aligned with product, cost, and scalability goals
• Lead chiplet-based packaging strategies including UCIe, silicon interposers, and advanced RDL
• Perform hands-on package design and physical layout for high-speed interfaces like PCIe, CXL, and LPDDR5
• Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines
• Drive SI/PI, thermal, mechanical, and reliability trade-offs
• Lead external engagement with OSATs, foundries, and key suppliers
• Establish scalable design methodologies and reusable packaging flows

Requirements

• BSEE or MSEE (PhD preferred) in Electrical Engineering or related field
• Minimum 10+ years of experience in IC packaging for SoCs, ASICs, or memory products
• Deep expertise in Flip-Chip BGA (FCBGA), SiP, RDL, and chiplet architectures (UCIe)
• Proven experience with high-speed SerDes package development (PCIe Gen5, LPDDR5/X, USB 3.x)
• Experience defining die-to-die and chiplet-based RDL/bump architecture
• Direct collaboration experience with OSATs, foundries, and substrate suppliers
• Proficiency with Cadence Allegro Package Designer (APD) or equivalent EDA tools

Preferred Qualifications

• SI/PI expertise including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer
• Experience building new packaging methodologies or platforms from scratch

About the Company

Axiado is building the future of AI powered digital infrastructure, pioneering the Trusted Control/Compute Unit (TCU) to secure critical infrastructure through advanced hardware security and AI-driven resilience.