Senior HV-BCD Device Expert

Responsibilities

• Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes
• Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI)
• Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles
• Define verification plans and execute statistical analysis using JMP for DOE and WAT data
• Work within Cadence environments for layout review and test structure design
• Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks

Requirements

• Master's or Ph.D. in EE, Physics, or a related field
• 10+ years of semiconductor industry experience
• Profound knowledge of Device Architecture and Device Physics
• Hands-on experience in 180nm to 55nm BCD process nodes
• Expertise in TCAD (Sentaurus / Silvaco)
• Expertise in JMP for statistical data analysis
• Proficiency in Cadence (Layout/Virtuoso)

Preferred Qualifications

• Experience with GaN, SiC, or IGBT development
• Knowledge of Silicon Photonics integration and device physics
• Understanding of Process Integration (PI) including mask flow and doping profiles
• Experience in Product Engineering (PE) regarding CP/FT data correlation and yield enhancement

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.