Senior FPGA Engineer

Responsibilities

• Own projects end-to-end, driving progression from inception, requirements, and architecture through design entry, timing closure, and verification
• Develop and maintain RTL using Verilog or SystemVerilog
• Write and maintain robust verification environments
• Design optimizations specifically for timing closure
• Partner with Low Latency, Trading, and other cross-functional teams to improve trading system performance and competitiveness
• Maintain comprehensive project documentation

Requirements

• 10+ years of experience in FPGA or ASIC digital logic design
• Deep proficiency in Verilog, SystemVerilog, or VHDL
• Solid grasp of static timing analysis, synthesis, and place-and-route tools
• Fluency in Python and Bash scripting
• Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field
• Familiarity with algorithms, data structures, and verification/unit testing workflows

Preferred Qualifications

• Experience with network traffic design
• Master's degree in a related engineering field
• Experience working in high-performance computing or low-latency environments

Benefits

• Competitive base salary and discretionary performance bonus
• Comprehensive medical, dental, and vision insurance
• Retirement contributions
• Paid time off and other employee benefits

About the Company

Akuna Capital is an innovative proprietary trading firm specializing in options market making. We focus on collaboration, cutting-edge technology, and data-driven solutions to provide liquidity to the global markets. We design and implement our own low-latency technologies, trading strategies, and mathematical models to maintain a competitive edge.