Senior FPGA Design Engineer

Responsibilities

• RTL design for FPGA, including RTL porting, IP integration, closing timing and generating bit streams
• FPGA simulation setup and testing
• FPGA system setup, validation and debug
• Work with SW team to bringup and validate FPGA system product

Requirements

• Product experience with FPGAs and related tools such as Vivado and Protocompiler
• Strong experience in RTL design, especially design for FPGAs
• Integration of IPs and CPUs for FPGA
• Experience in RTL simulation testing
• Experience in bringing up and debugging SW on FPGA systems
• Familiarity with PCIe, USB, Ethernet, SPI
• BS or MS degree in EE/EECS/CS or equivalent
• At least 5 years of industrial experience

Preferred Qualifications

• Knowledge of ESPI, SGPIO, LTPI
• Prior knowledge of computer architecture

About the Company

Axiado is building the future of AI-powered digital infrastructure. We are a fast-growing, well-funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI-driven resilience and efficiency, and real-time platform management.