Senior FPGA Design Engineer

Responsibilities

• Participate in architecture definition, implementation, and test plan development
• Develop and implement RTL level blocks
• Perform synthesis and implement on FPGAs
• Resolve timing violations
• Coordinate with Software and Hardware teams to identify and resolve system issues

Requirements

• 5+ years of work experience
• 2+ years of experience in team leadership
• Strong base in digital design, RTL, and FPGA development flows
• Proficiency in SystemVerilog or Verilog for RTL Design
• Experience building IPs using AXI4, AXI4 Lite, and AXI4 Stream protocols
• Understanding of Xilinx FPGA Architecture and Vivado tools
• Knowledge of digital signal processing techniques like Fast Fourier Transform
• Familiarity with engineering processes such as JIRA and Git

Preferred Qualifications

• Strong handle on linear algebra and complex algebra
• Understanding of baseband realization for wireless systems such as OFDM

Benefits

• Career growth opportunities
• ESOPs
• Gratuity
• PF
• Health Insurance