Senior FPGA Compiler (Router) Engineer

Responsibilities

• Design, implement, and optimize FPGA routing algorithms to improve performance, routability, and timing closure
• Contribute to the FPGA compiler flow, including placement, routing, and timing-driven optimization
• Analyze and improve runtime, memory efficiency, and scalability of routing algorithms for large designs
• Collaborate with architecture, synthesis, timing (STA), and hardware teams to align routing strategies with device capabilities
• Investigate routing congestion, timing violations, and design bottlenecks to develop convergence solutions
• Integrate routing features into existing compiler infrastructure and ensure robustness across diverse use cases

Requirements

• 9+ years of experience in FPGA/ASIC design tools, EDA, or related fields
• Strong background in algorithms and data structures, specifically graph algorithms and optimization techniques
• Experience with FPGA or ASIC design flows, including placement, routing, and timing closure
• Proficiency in C/C++ and software development best practices
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Familiarity with routing algorithms (e.g., maze routing, negotiated congestion) and physical design concepts

Preferred Qualifications

• Experience with commercial FPGA toolchains such as Quartus or Vivado
• Knowledge of FPGA architectures and interconnect fabrics
• Familiarity with parallel/distributed computing for EDA workloads
• Experience with scripting languages like Python or Tcl for tooling and automation
• Background in timing analysis or placement algorithms

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs, and IPUs.