Senior Engineer - Static Timing Analysis

Responsibilities

• Own end-to-end full-chip STA signoff using Synopsys PrimeTime (PT / PT-SI) across all design modes and corners
• Execute MMMC (Multi-Mode Multi-Corner) analysis across full PVT space using OCV, AOCV, and POCV methodologies
• Author, maintain, and audit full-chip SDC constraints, including clock definitions, I/O delays, and timing exceptions
• Drive timing convergence and closure in collaboration with P&R, synthesis, and RTL teams
• Perform timing checks in Low Power Modes (UPF/CPF, power domains) and conduct Signal Integrity (SI) analysis
• Support RTL synthesis runs using Design Compiler and provide timing-driven feedback to improve QoR
• Establish and track timing closure metrics such as WNS, TNS, and failing endpoint counts

Requirements

• B.Tech, M.Tech, or M.S. in Electronics Engineering, VLSI Design, or Computer Engineering
• 8+ years of professional experience in STA or timing closure roles
• Expert-level proficiency with Synopsys PrimeTime
• Deep expertise in SDC constraint authoring and auditing
• Proven experience with MMMC, OCV, AOCV, and POCV methodologies
• At least one successful tape-out on 7nm process nodes or below
• Proficiency in Tcl scripting

Preferred Qualifications

• Familiarity with P&R tools for timing-driven closure
• Understanding of PTPX-based power and timing co-analysis
• Exposure to formal CDC/RDC verification tools like SpyGlass or VC SpyGlass
• Knowledge of Clock Tree Synthesis (CTS) and its impact on timing
• Background in Liberty (.lib) characterization and NLDM/CCS models
• Proficiency in Python scripting

About the Company

Ericsson is a global leader in telecommunications, driving the future of 5G and 6G networks. We build the pioneering digital ASIC designs that power mobile network infrastructure, fostering an innovative environment focused on quality, teamwork, and continuous career development.