Senior Engineer, Physical Design Floorplan

Responsibilities

• Drive top-level floorplan execution and block-level floor-planning
• Execute key floor-planning activities including placement, shaping, pinning, and methodology
• Collaborate with Architecture, RTL, PPA, and Physical Design teams to optimize PPA aspects
• Work with CAD teams to continuously improve floor-planning design methodologies
• Lead physical-verification convergence of the top-level floorplan to achieve final GDS delivery

Requirements

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field
• 5+ years of professional experience (or 3+ years with a Master's, or 1+ year with a PhD)
• Proficiency in EDA flows, methodologies, and industry standards for floor-planning
• Expertise in Top and Block level Floor-planning techniques such as partitioning, pinning, and budgeting
• Experience with power-grid implementation and clock distribution
• Strong scripting and automation skills in Python, TCL, Shell, or Perl
• Hands-on experience delivering final GDS for high-performance IPs and SOCs

Preferred Qualifications

• Strong understanding of sign-off closure flows in deep-submicron technology
• Experience in physical verification, STA, EMIR, and Power domains

Benefits

• Medical, dental, and vision insurance
• 401(k) and life insurance
• Onsite lunch and employee purchase programs
• Tuition assistance and student loan programs
• Paid time off and wellness incentives
• Eligibility for MBO bonus compensation and long-term incentive plans

About the Company

Samsung Electronics is a global leader in technology, transforming the worlds of smartphones, wearable devices, and the semiconductor industry. Through the Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we build high-performance computing IP applied to mobile, automotive, and custom market segments consumed by millions worldwide.