Senior Engineer, ASIC DFT

Responsibilities

• Accountable for innovative DFT implementation (Scan, MBIST, LBIST, and Boundary Scan) at the RTL and Gate level for SOCs at Hard macro and chip top levels.
• Generate and validate ATPG patterns using simulations.
• Validate DFT implementation using RTL and Gate level simulation.
• Collaborate with multi-functional teams on STA, Synthesis, LEC, CLP, verification, and validation.
• Support silicon bring-up activities to ensure the highest stability of test patterns and programs.
• Contribute to the overall development of DFT methodologies.

Requirements

• Bachelor's or Master's degree in Electronics Engineering, Microelectronics, Software Engineering, or a related field.
• 5+ years of industry experience in DFT of highly sophisticated SOCs.
• Expertise in Scan Codec insertion, MBIST/Repair implementation, LBIST, ATPG, BSCAN, and JTAG (IEEE1149.1 & IEEE1687).
• Experience with fault simulation, ATPG fault models (SAF, TDF, SDD, PDT, etc.), and SDF annotated gate level verification.
• Hands-on experience with Siemens, Synopsys, or Cadence EDA tools.
• Proficiency in coding with Verilog, VHDL, C/C++, TCL, Perl, or Python.

Preferred Qualifications

• Knowledge of IEEE 1149.6, 1500, and 1838 standards.
• Experience with Hierarchical Scan implementations and core wrapping concepts.
• Experience handling multi-clock domains and low power design implementation.
• Knowledge of SSN, 2.5D, or 3D IC DFT implementation.

Benefits

• Competitive compensation and multiple Micron benefits.
• Paid Time Off (PTO).
• Comprehensive medical benefits.

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. We deliver a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products, enabling advances in artificial intelligence, 5G, and the data economy.