Senior Engineer, ASIC Development Engineering (STA, Sign Off)

Responsibilities

• Own Subsystem level STA, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
• Develop and implement advanced STA methodologies and strategies to meet timing closure requirements
• Collaborate with cross-functional teams including design, verification, physical design, and DFT
• Drive development and maintenance of STA scripts and tools to automate processes
• Conduct thorough timing analysis, identify critical paths, and mitigate timing violations
• Prepare and present detailed timing reports and technical documentation to stakeholders

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Minimum of 2 years of experience in Static Timing Analysis
• Proven track record of successfully executing STA
• In-depth knowledge of STA tools such as Synopsys PrimeTime, Cadence Tempus, and Constraints Manager
• Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
• Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

About the Company

Sandisk understands how people and businesses consume data and relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas through groundbreaking innovations in Flash and advanced memory technologies.