Senior Engineer, ASIC Development Engineering (IP Verification)

Responsibilities

• Design complex logic blocks and IPs within a multi-disciplinary environment.
• Develop FPGA solutions for post-silicon validation of memory devices.
• Build testbenches for constrained-random and metric-driven verification.
• Root-cause design issues and communicate technical findings clearly.
• Automate flows, logs, and regressions using scripting.
• Leverage new technologies, including AI/ML, to improve verification efficiency and workflows.

Requirements

• BE/ME in ECE, Electronics, or a related engineering discipline.
• 5 years of hands-on experience in RTL verification at Block, IP, Sub-system, or SoC levels.
• Proficiency in SystemVerilog for verification.
• Experience with FPGA-based verification environments.
• Deep knowledge of EDA tools such as Cadence (NCSim, SimVision, vManager), Mentor, or Synopsys.
• Proficiency in Perl or Python scripting.
• Familiarity with version control systems such as Git.

Preferred Qualifications

• Advanced experience with SVA and UVM.
• Exposure to standard protocols such as eMMC, UFS, USB, PCIe, and DDR4.
• Understanding of AI/ML fundamentals applied to hardware verification workflows.
• Experience using ML techniques for regression triage, failure clustering, or coverage prediction.

About the Company

Sandisk relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions are the beating heart of the digital world. We are committed to an inclusive environment where diversity of perspective drives the best outcomes for our employees and customers.