Senior Digital Verification Engineer

Responsibilities

• Architect and execute comprehensive verification strategies and test plans
• Implement UVM-based environments from scratch
• Drive functional and code coverage to closure using constrained-random testing and assertion-based verification (SVA)
• Review design specifications early in the cycle to ensure fitness for verification
• Partner with global architecture, design, and software teams to optimize system-level verification
• Mentor junior engineers and champion design/verification reviews
• Evaluate third-party VIP and tools to optimize engineering efficiency

Requirements

• Extensive experience in ASIC/IC digital verification
• Mastery of SystemVerilog and UVM
• Proven ability to independently set up a UVM testbench from scratch
• Proficiency with Cadence Xcelium and eManager/vManager
• Strong knowledge of Verilog and VHDL
• Solid grounding in Functional Verification, ABV, Formal Verification, and regression frameworks
• Intermediate to advanced digital design skills
• Excellent English communication skills (written and verbal)

About the Company

Renesas is an embedded semiconductor solution provider driven by its purpose "To Make Our Lives Easier." As a leading expert in embedded processing, we provide scalable semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. With a diverse team of over 21,000 professionals in more than 30 countries, we design sustainable, power-efficient solutions that help communities thrive.