Senior Digital Verification Engineer

Responsibilities

• Architect and execute comprehensive verification strategies, test plans, and UVM-based environments from scratch
• Drive functional and code coverage to closure using constrained-random testing, assertion-based verification (SVA), and formal methods
• Review design specifications early in the cycle to improve quality and fitness for verification
• Partner with global architecture, design, and software teams to optimize hardware/software partitioning
• Mentor junior engineers and champion design/verification reviews
• Evaluate third-party VIP and tools to optimize engineering efficiency

Requirements

• Extensive experience in ASIC/IC digital verification
• Mastery of SystemVerilog and UVM
• Proven ability to independently set up a UVM testbench from scratch
• Proficiency with Cadence Xcelium and eManager/vManager
• Knowledge of Verilog and VHDL
• Strong grounding in Functional Verification, ABV, and Formal Verification
• Excellent English proficiency (written and verbal)

Preferred Qualifications

• Intermediate to advanced digital design skills for deep technical alignment with architecture teams
• Experience with regression frameworks and automation flows

Benefits

• Opportunities to launch and advance your career across various product groups and corporate functions
• A flexible and inclusive work environment with a people-first culture
• Global support systems and Employee Resource Groups

About the Company

Renesas is an embedded semiconductor solution provider driven by its purpose "To Make Our Lives Easier." As a leading expert in embedded processing, Renesas provides scalable semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. With over 21,000 professionals in more than 30 countries, we design sustainable, power-efficient solutions that help communities thrive.