Senior Digital Verification Engineer

Responsibilities

• Read and understand architecture and functional requirements to collaborate with systems engineers and architects
• Validate architectural functional blocks using simulation, formal, and coverage methods
• Develop verification, functional coverage, and formal verification test plans
• Create testbench environments, components, agents, scoreboards, and test scenarios using SystemVerilog UVM and/or C
• Perform coverage-driven verification, monitor regressions, and debug failures
• Provide regular status updates on verification progress

Requirements

• 5+ years of relevant industry experience
• Bachelor's degree in Electrical or Computer Engineering
• Significant experience with SystemVerilog, UVM, SVA, and major vendor simulators
• Proven ability to determine comprehensive digital verification and coverage strategies

Preferred Qualifications

• Experience with formal verification methods
• Familiarity with Python, Make, bash, C, or C++
• Proficiency with Jira for bug tracking and GIT for source code management
• Knowledge of digital analog converters and PLLs

Benefits

• Comprehensive medical, dental, and vision plans
• Retirement savings plans (401(K) or DCPP) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Paid sick leave and vacation time

About the Company

Ciena is a global leader in high-speed connectivity, committed to a people-first approach. We drive business priorities alongside meaningful social, community, and societal impact, fostering a culture that prioritizes flexibility, individual growth, and belonging.