Senior Digital Design Engineer

Responsibilities

• Own end-to-end physical implementation for major IP blocks and full-chip designs.
• Develop and optimize floorplans, including macro placement, IO ring planning, and power grid design.
• Execute place-and-route (PNR), clock tree synthesis (CTS), and timing closure using industry-standard tools like Cadence Innovus.
• Perform detailed static timing analysis (STA) and drive sign-off across various PVT corners.
• Identify and resolve physical verification issues (DRC/LVS/ERC) in partnership with foundry teams.
• Automate design flows using Tcl, Perl, or Python to improve efficiency and quality.
• Collaborate with RTL, DFT, and verification teams to meet PPA (Power, Performance, Area) targets.
• Mentor junior engineers and document methodologies to support continuous improvement.

Requirements

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related discipline.
• 5+ years of hands-on experience in ASIC/SoC physical design.
• Proven experience working with advanced process nodes (e.g., 40nm, 28nm, 22nm, 16nm).
• Strong proficiency in floorplanning, PNR, STA, and physical verification using EDA tools.
• Experience developing or deploying automated design flows using Tcl, Perl, or Python.
• Deep understanding of fabrication process limitations, ESD/IR/EM analysis, and sign-off methodologies.

Preferred Qualifications

• Experience with hierarchical design and large-scale SoC integration.
• Sound knowledge of EDA synthesis and formal equivalence checking.
• Background in low power and multi-voltage design methodologies (UPF/CPF).

About the Company

Analog Devices, Inc. (ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. We combine analog, digital, AI, and software technologies into solutions that drive advancements in automation, robotics, mobility, healthcare, and energy.