Senior Digital ASIC Design Engineer

Responsibilities

• Contribute to top-level ASIC design and integration for WaveLogic products
• Interpret architecture and functional specifications in collaboration with systems engineers and architects
• Develop and assemble top-level RTL designs by integrating multiple IP blocks
• Maintain and enhance technology-specific libraries for advanced semiconductor nodes
• Own and manage tool flows supporting ASIC top-level integration
• Create timing constraints and analyze synthesis, timing, layout, and backend reports
• Perform lab validation of ASIC prototypes and production silicon

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
• 5+ years of experience in ASIC design
• Proficiency in Verilog, SystemVerilog, and Python within digital design workflows
• Strong understanding of digital design concepts including synthesis, static timing analysis (STA), timing closure, and asynchronous clock domain crossing
• Ability to work independently and solve complex technical problems using structured approaches
• Excellent written and verbal communication skills in English

Preferred Qualifications

• Exposure to programming languages such as C, C++, and SystemC
• Experience using scripting or object-oriented programming approaches in engineering workflows
• Experience with ASIC verification

Benefits

• Competitive annual pay range
• Comprehensive medical, dental, and vision plans
• Retirement savings plans (401(K) in USA or DCPP in Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Paid sick leave, vacation time, and company-paid holidays
• Employee Assistance Program (EAP)

About the Company

Ciena is a global leader in high-speed connectivity, dedicated to advancing high-performance optical networking solutions. Through our WaveLogic products, we power critical telecommunications infrastructure. We prioritize a people-first culture that emphasizes flexibility, individual growth, and meaningful societal impact.