Senior DFT Engineer

Responsibilities

• Develop detailed test plans for new DFT features and automate test cases using Verilog, System Verilog, or VHDL
• Review specifications and test plans from Product Engineering and R&D teams to ensure feature completeness
• Collaborate with cross-functional teams to implement scalable DFT solutions tailored to customer architectures
• Build and validate prototype test flows and reference designs for compression, ATPG, and Memory/Logic BIST
• Perform Quality of Results analysis and root cause analysis to resolve complex issues across the ASIC flow
• Conduct diagnostics analysis and debugging to improve tool reliability and performance
• Work with AI agents to create assistive or generative AI documentation for test products

Requirements

• Bachelor's, Master's, or MTech in Electrical/Electronics Engineering, Computer Science, or a related field
• 3+ years of relevant experience in DFT or ASIC test
• Hands-on expertise in DFT technologies such as JTAG, MBIST, Scan, and ATPG
• Proficiency in RTL coding using Verilog, System Verilog, and/or VHDL
• Advanced scripting skills in Python, Perl, Tcl/Tk, or similar languages
• Solid understanding of ASIC design flow, including synthesis, physical design, and sign-off verification

Preferred Qualifications

• Familiarity with change management tools like Perforce
• Experience with DFT compression, diagnostics, or AI-enabled test automation

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Competitive total rewards including both monetary and non-monetary offerings

About the Company

Synopsys drives the innovations that shape the way we live and connect. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content for the Era of Pervasive Intelligence.