Senior DFT Engineer

Responsibilities

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan
• Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies
• Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns
• Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches and analog test interfaces
• Collaborate with RTL, DV, and PD teams to ensure clean DFT integration and timing alignment
• Drive DFT verification and signoff, including Scan/ATPG coverage metrics and gate-level simulation
• Support bring-up and silicon debug activities by analyzing tester failures and yield issues

Requirements

• B.S. or M.S. in Electrical Engineering or related field
• 7+ years of experience in DFT for complex SoCs
• Strong hands-on experience with RTL DFT insertion and ATPG tools
• Deep understanding of scan architectures, compression techniques, and fault models
• Experience with low-power DFT techniques
• Familiarity with mixed-signal integration challenges
• Strong debugging skills across RTL, gate-level, and silicon

Preferred Qualifications

• Experience with MBIST/LBIST implementation and memory repair flows
• Knowledge of IEEE 1149.x (JTAG/boundary scan) standards
• Experience with multi-voltage domain and power-aware DFT
• Scripting experience for automation
• Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs
• Prior involvement in A0 silicon bring-up and yield ramp

About the Company

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by leading investors, K2 is mass-producing high-power satellite platforms for missions from LEO to deep space.