Senior Design Verification Engineer

Responsibilities

• Define, plan, and implement block and system level verification strategies
• Write and review test plans, develop test harnesses and test sequences
• Drive the design verification process to successful closure by meeting defined verification metrics across the test plan, functional coverage, and code coverage
• Collaborate closely with the Design team to debug, root-cause, and resolve functional failures within the design
• Work collaboratively with cross-functional teams, including Design, Model, Emulation, and Silicon Validation, to ensure the highest standards of design quality

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or a closely related technical field
• 5+ years of experience in block and system level verification utilizing SystemVerilog/UVM-based methodologies
• Proven experience with Electronic Design Automation (EDA) tools
• Proficiency in scripting languages such as Python, Perl, or Shell
• Experience architecting and deploying Design Verification infrastructure from planning to closure

Preferred Qualifications

• Master’s degree in Electrical Engineering or Computer Science
• Expertise in developing UVM-based verification environments from initial setup
• Expertise in developing Python-based verification environments such as cocotb
• Experience in IP or integration verification for high-speed interfaces (PCIe, UCIe, UALink, Ethernet)
• Experience verifying ARM/RISC-V-based sub-systems or SoCs