Senior Design Verification Engineer

Responsibilities

• Verify mixed-signal designs and sub-systems using leading-edge verification methodologies
• Develop directed and constrained random test cases in SystemVerilog
• Implement and manage complete metric-driven SystemVerilog and UVM verification environments
• Define test plans, tests, and verification methodologies for block and chip-level verification
• Collaborate with analog and digital teams to enable top-level chip verification
• Support post-silicon verification activities in coordination with design and applications engineering teams

Requirements

• BSEE with 5+ years of experience or MSEE with 1+ years of experience in Digital and/or Mixed-Signal IC verification
• Strong fluency in SystemVerilog within the verification domain
• Proven experience developing testbenches and testcases using SystemVerilog and UVM
• Proficiency in object-oriented programming and strong coding skills
• Experience with SystemVerilog Assertions (SVA) for dynamic and formal verification
• Knowledge of test-plan generation, coverage analysis, and constrained random techniques
• Ability to execute the entire digital verification process independently

Preferred Qualifications

• Experience with mixed-signal simulation (Cadence AMS) and interfacing with analog functions
• Proficiency in scripting languages such as Python, Perl, or C
• Experience writing Verilog-AMS and Real Number Models (RNM) for analog functions
• Knowledge of custom digital interfaces including I2C, SPI, and UART
• Experience verifying ARM/RISC-V based sub-systems or SoCs
• Familiarity with multiphase DC-DC controllers and voltage interfaces like PMBUS or AVS

About the Company

Analog Devices, Inc. (ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. We combine analog, digital, AI, and software technologies into solutions that combat climate change, connect humans, and drive advancements in automation, mobility, healthcare, and energy.