Senior Design Verification Engineer

Responsibilities

• Collaborate with architects and design engineers to define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM.
• Create and implement directed and random test cases to exercise design functionality and uncover potential bugs.
• Develop verification components including drivers, monitors, scoreboards, and checkers.
• Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection.
• Execute simulation regressions, debug test failures, and analyze root causes.
• Define and track functional and code coverage metrics to ensure verification completeness.
• Develop automation scripts and infrastructure using Python or Perl to improve verification efficiency.

Requirements

• Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or a related field.
• 10+ years of experience in ASIC or FPGA design verification.
• Expertise in Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.
• Strong hands-on experience developing UVM-based testbenches and verification components.
• Proficiency in coverage-driven verification (CDV) and assertion-based verification (ABV).
• Experience with simulation and debug tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.
• Excellent analytical, problem-solving, and debugging skills.

Preferred Qualifications

• Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet.

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.