Senior Debug Verification Engineer at Altera - ScoutJobs - The AI-curated global job board
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Posted 17 days ago

Senior Debug Verification Engineer

AlteraSenior Debug Verification Engineer

Requirements

8+ years complex ASIC design/verification, 8+ years SystemVerilog, 8+ years UVM methodology, 8+ years Linux/Unix scripting, Proficiency in Perl or Python

Skills

UVMSystemVerilogASICPythonPerl

About the role

Responsibilities

  • Perform pre-silicon system verification for SoC, FPGA, and full chip designs
  • Create test cases and test benches using UVM methodology
  • Define verification strategies, methodologies, and test plans for full-chip and system functional verification
  • Verify Design for Debug architectures, including JTAG, High-speed USB, PCIe-based debug, and internal signal visualization
  • Coordinate cross-functional efforts with Design, Software, and Architecture teams to achieve full coverage verification plans
  • Use system full applications to verify performance and identify shortfalls

Requirements

  • 8+ years of experience with complex ASIC design and/or verification
  • 8+ years of experience with SystemVerilog
  • 8+ years of experience with UVM verification methodology and formal verification methods
  • 8+ years of experience scripting in Linux/Unix environments
  • Proficiency in Perl or Python
  • Strong communication skills and ability to work with geographically distributed teams

Preferred Qualifications

  • Experience with ARM and RISC Debug Architectures
  • Prior experience with UltraSoC or Tessent Embedded Analytics Debug Architecture
  • Experience with Emulation

About the Company

Altera is the world’s largest pure-play FPGA solutions provider, delivering programmable technologies that help customers innovate across AI, cloud, networking, and edge markets. With over four decades of industry expertise, Altera provides an end-to-end portfolio including FPGAs, CPLDs, Intellectual Property, and development tools.

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Senior Debug Verification Engineer

Altera · San Jose

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