Senior Custom SOC IP Verification Engineer

Responsibilities

• Responsible for ASIC design verification for various IPs at both IP and SOC levels
• Develop and integrate reference models
• Participate in IP/SOC architecture and micro-architecture reviews
• Interface with Architecture, SW/FW, Design, and Modeling teams to create comprehensive verification plans
• Contribute to innovative verification methodology development and functional/code coverage closure
• Create complex testbenches and execute direct/random tests to drive coverage closure
• Contribute to silicon and platform verification strategies
• Triage SOC-level failures in collaboration with SOCV, EMU, and SW teams
• Support soft and hard IP identification, selection, and licensing processes

Requirements

• B.S. or M.S. degree in Computer Engineering or Electrical Engineering
• 5+ years of experience owning processing ASIC, IP, or SoC design verification
• Experience managing and delivering complex mixed-language UVM and C++ testbenches
• Proficiency in C++ and SystemC, including familiarity with GDB debugging
• Experience developing tools and infrastructure using Perl or Python
• Strong understanding of design verification tools such as Synopsys VCS, Cadence Xcelium, Verdi, JasperGold, or VC Formal
• Proven ability to interpret functional specifications and create comprehensive test plans
• Ability to write directed and constraint-random tests for coverage-driven verification

Preferred Qualifications

• Hands-on background with AMBA protocols (AXI, ACE, CHI, etc.)
• Experience with complex subsystems including ARM CPU complexes, LPDDR, HBM, GPUs, UCIe, PCIe, or Network on Chip (NoC)
• Experience with performance verification

About the Company

NVIDIA NVLink™ Fusion delivers industry-leading AI scale-up and scale-out performance by combining NVIDIA technology with semi-custom ASICs or CPUs.