Senior ASIC Verification Engineer

Responsibilities

• Propose and implement innovative verification strategies to simulate and validate functional blocks and subsystems for the Wavelogic product family
• Read and interpret architecture and functional requirement specifications to collaborate with systems engineers and architects
• Execute complete validation of architectural functional blocks using simulation, formal, and coverage methods
• Contribute to verification planning, functional coverage definition, and formal verification test plans
• Create or integrate test bench environments, including components, agents, scoreboards, and test scenarios using SystemVerilog UVM and/or C
• Perform coverage-driven verification, monitor regressions, and debug failures in collaboration with designers
• Provide regular status updates on verification progress

Requirements

• BEng, BSc, MEng, or MSc in Electrical Engineering, Computer Engineering, Computer Science, or a related scientific field
• Proficiency in SystemVerilog, UVM, and SVA
• Experience with major vendor simulators
• Proven ability to develop and resolve comprehensive digital verification and coverage strategies
• Strong organizational, written, and oral communication skills in English
• Ability to work independently as a self-starter while contributing effectively to a team

Preferred Qualifications

• Experience with formal verification methods
• Knowledge of industry standards and protocols such as OTN, FlexO, B100G, or Ethernet (100GE+)
• Experience with GIT for source code management and Jira for project tracking
• Familiarity with programming languages including Python, C, C++, Make, or Bash

About the Company

Ciena is a global leader in high-speed connectivity, providing innovative optical fiber transmission solutions. We are committed to a people-first approach, fostering a flexible work environment that prioritizes individual growth, well-being, and belonging while driving meaningful societal impact.