Senior ASIC Digital Engineer (SOC Design)

Responsibilities

• Define and review SoC architecture and design specifications
• Develop high-quality synthesizable RTL using Verilog/SystemVerilog
• Ensure robust design methodologies including lint, CDC, RDC, and FC-Elab
• Partner with cross-functional teams including Verification, DFT, Physical Design, and Firmware
• Provide technical leadership and mentorship to engineering teams
• Drive integration and debug efforts for subsystem and full-chip levels
• Analyze design trade-offs for area, performance, and power optimization
• Contribute to IP selection, evaluation, and integration

Requirements

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
• 5–8 years of experience in digital design and SoC RTL design/integration
• Deep expertise in Verilog/SystemVerilog
• Strong understanding of SoC architecture and AMBA protocols (AXI/AHB/APB)
• Experience with synthesis, static timing analysis, and DFT concepts
• Proficiency with EDA tools for simulation, lint, CDC, and formal verification
• Experience with version control systems like Perforce or Git

Preferred Qualifications

• Experience with high-speed interfaces such as PCIe and LPDDR5
• Expertise in low-power design techniques
• Familiarity with scripting languages including Perl, Python, TCL, or Shell
• Experience with silicon bring-up and post-silicon validation

About the Company

Sandisk understands how people and businesses consume data and relentlessly innovates to deliver solutions that enable today’s needs and tomorrow’s next big ideas through groundbreaking innovations in Flash and advanced memory technologies.