Senior ASIC Design Verification Engineer

Responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models
• Write SystemVerilog Assertions (SVA) and integrate formal verification
• Drive constrained-random and directed testing strategies
• Run simulations, triage failures, and collaborate with RTL designers to resolve issues
• Implement and maintain functional, code, and assertion coverage
• Manage regression testing, simulation farms, and CI pipelines
• Participate in design reviews and influence design-for-verification (DFV) best practices
• Support silicon bring-up and post-silicon validation

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in ASIC/SoC verification
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows
• Proficiency with simulation tools (VCS, Xcelium, Questa) and waveform debug (Verdi, SimVision)
• Experience with UVM-based testbench development and constrained-random testing
• Experience with regression management, Git, and CI/CD automation
• Understanding of industry-standard interfaces like APB, AHB, or AXI
• Familiarity with embedded processor-based designs and C/C++

Preferred Qualifications

• Experience developing and integrating reference models
• Understanding of low power verification
• Familiarity with gate-level simulation and analog behavioral models
• Involvement in post-silicon validation planning
• Experience in space, telecom, or RF/digital mixed systems

About the Company

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by leading investors, K2 is mass-producing high-power satellite platforms for missions from LEO to deep space.