Senior Analog Engineering Manager

Responsibilities

• Lead the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.
• Provide technical oversight for high-speed TX/RX datapaths, equalization, and DLL/PLL-based clocking solutions.
• Manage a team of analog and mixed-signal designers, setting technical direction and development plans.
• Drive hiring, onboarding, and team scaling to meet DDR5 production and DDR6 development needs.
• Partner with cross-functional teams including Digital PHY, SoC integration, Package, and SI/PI to ensure successful delivery.
• Lead post-silicon bring-up, characterization, and debug to improve yield and performance.
• Establish robust design methodologies and drive the long-term DDR technology roadmap.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering (PhD preferred).
• 12+ years of experience in analog/mixed-signal IC design with a focus on high-speed memory interfaces.
• 5+ years of people-management and technical leadership experience.
• Proven track record of delivering DDR5 PHYs or transitioning DDR4 designs to DDR5.
• Deep expertise in high-speed IO design, signal integrity, and PLL/DLL architectures.
• Strong understanding of mixed-signal verification and silicon validation.

Preferred Qualifications

• Direct involvement in DDR6 architectural studies or early-stage development.
• Experience working with advanced CMOS process nodes (7nm, 5nm, and below).
• Background in developing multi-generation memory PHYs or scalable PHY platforms.
• Ability to lead teams through multiple concurrent tape-outs.

About the Company

Renesas is an embedded semiconductor solution provider driven by the purpose "To Make Our Lives Easier." As a leading expert in embedded processing, we provide scalable semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. With a global team of over 22,000 professionals, we design innovative, power-efficient solutions that help communities thrive.