Scientist- ASIC Verification, Interface IP- PCIe/CXL

Responsibilities

• Define and architect RTL verification strategies for Interface IP controllers, focusing on PCIe, CXL, and UCIe protocols.
• Build and own scalable testbench architectures using UVM and advanced verification methodologies.
• Develop comprehensive verification plans that map protocol specifications to coverage models and real-world system interactions.
• Debug complex protocol interactions and root-cause issues spanning RTL, testbench, and tooling.
• Mentor verification engineers by reviewing test plans, guiding debug sessions, and establishing best practices.
• Collaborate with cross-functional teams globally to ensure verification quality and consistency.

Requirements

• 20+ years of hands-on experience in ASIC RTL verification with a track record of shipping complex digital designs.
• Deep expertise in PCIe (Gen 3 through Gen 6), CXL (1.x, 2.0, or 3.0), or UCIe protocol verification.
• Proven ability to define and execute testbench architecture using SystemVerilog, UVM, and constrained-random verification.
• Strong command of verification planning, coverage modeling, assertion-based verification, and formal methods.
• Demonstrated ability to mentor engineers and lead technical discussions across global teams.
• Excellent communication skills to explain complex verification tradeoffs to architects and product managers.

Benefits

• Comprehensive medical and healthcare plans.
• Paid time away including ETO and FTO programs.
• Family support including maternity/paternity leave and adoption assistance.
• Employee Stock Purchase Plan (ESPP) with a 15% discount.
• Competitive salaries and regional retirement plans.

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across the semiconductor industry.