RTL Intern

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.

Responsibilities

• Help design microarchitecture and implement logic in Verilog
• Work with cutting-edge machine learning architectures
• Contribute to RTL block development
• Participate in the full design cycle from microarchitecture discussions to synthesis and timing feedback

Requirements

• Progress towards a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or a related field
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling
• Ability to learn quickly about transformers and modern AI

Preferred Qualifications

• Familiarity with modern ML and LLM model architectures
• Familiarity with numerical representations and functions
• Familiarity with clocking and reset schemes
• Ability to program with Python or another scripting language

Benefits

• 12-week paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Direct mentorship from industry leaders and world-class engineers