RTL Intern

Responsibilities

• Design microarchitecture and implement logic in Verilog for cutting-edge ML hardware
• Contribute to RTL block development across the full design cycle
• Participate in microarchitecture discussions, synthesis, and timing feedback
• Work in a fast-paced, high-autonomy environment

Requirements

• Progress towards a Bachelor’s, Master’s, or PhD in electrical or computer engineering
• Familiarity with high-speed digital logic and ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling

Preferred Qualifications

• Familiarity with modern ML and LLM model architectures
• Familiarity with numerical representations and functions
• Familiarity with clocking and reset schemes
• Ability to program with Python or another scripting language

Benefits

• 12-week paid internship with generous housing support for relocating interns
• Daily lunch and dinner provided in the San Jose office
• Direct mentorship from industry leaders and world-class engineers

About the Company

Etched builds hardware for frontier intelligence, co-designing chips, racks, software, and manufacturing to deliver best-in-class throughput and latency for AI inference. Backed by top-tier investors and staffed by leading engineers, Etched is a fully in-person team based in San Jose.