RTL Engineer

Responsibilities

• Own RTL design of digital blocks and subsystems for the AI accelerator
• Translate architectural specs into efficient, synthesizable RTL meeting PPA targets
• Drive microarchitecture trade-offs including pipelining, datapath, and clock/power gating
• Partner with DV, PD, and DFT teams across the full design flow
• Manage block-level quality including synthesis, timing constraints, lint, and CDC signoff
• Contribute to architecture definition and debug across simulation, emulation, and post-silicon bring-up
• Use and develop AI-assisted tool flows to accelerate design and verification

Requirements

• Strong digital-design fundamentals
• Expert Verilog/SystemVerilog RTL skills
• 5+ years designing complex digital blocks or SoCs taken to silicon
• Solid microarchitecture skills (pipelining, FIFOs, arbitration, memory subsystems, NoC)
• Synthesis and timing awareness (SDC, STA, CDC, lint)
• Experience collaborating across the RTL2GDS flow to tapeout
• Scripting proficiency in Python or Tcl

Preferred Qualifications

• AI/ML accelerator or high-performance compute-datapath design experience
• Knowledge of low-power techniques (UPF)
• Experience with high-speed interfaces (HBM, PCIe, SerDes)
• Experience with advanced nodes (7nm or better)
• RISC-V/CPU design or FPGA prototyping experience