RTL Design Engineer

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs
• Participate in the full ASIC/FPGA design lifecycle from architecture to lab bring-up
• Engage in high-level architectural design for FPGA and ASICs
• Collaborate with cross-functional engineers to develop new technologies for User terminals and Satellites

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
• 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
• Ability to work extended hours or weekends as needed for mission critical deadlines

Preferred Qualifications

• Master’s in Electrical/Computer Engineering or related field
• ASIC/FPGA system integration experience
• Proficiency in Python for scripting
• Experience in designing DSP or digital communication system datapath blocks
• Experience with EDA tools such as HDL simulators
• Experience and understanding of AXI/AHB/APB protocols

Benefits

• Long-term incentives including company stock, stock options, or long-term cash awards
• Comprehensive medical, vision, and dental coverage
• 401(k) retirement plan
• Short and long-term disability insurance
• Life insurance
• Paid parental leave
• 3 weeks of paid vacation and 10+ paid holidays
• Employee Stock Purchase Plan