RTL Design Engineer

Responsibilities

• Perform low power RTL design, microarchitecture, synthesis, timing closure, and power estimation
• Optimize microarchitecture and RTL for area and power reduction (PPA analysis)
• Work on SoC integration and optimization of arithmetic units or floating point data paths
• Utilize ASIC design tools including VCS, Verdi, and Design Compiler
• Manage power estimation using tools such as Spyglass or PTPX
• Sign off RTL and synthesized netlists for Physical Design and tape-out processes

Requirements

• 6-10 years of experience in low power RTL design and microarchitecture
• Proficiency in Verilog and System Verilog
• Hands-on experience with AXI and APB bus protocols
• B.Tech, B.E, M.Tech, or M.E degree in a relevant field
• Experience with ASIC design tools (VCS, Verdi, Design Compiler)

Preferred Qualifications

• Experience with PCIe or UCIe protocols
• Prior domain experience in Artificial Intelligence or Near Memory acceleration
• Knowledge of scripting languages such as Shell, Perl, Python, or C
• Experience with hardware architecture exploration and performance modeling

About the Company

Samsung Semiconductor India Research (SSIR) is a major R&D center for Samsung Electronics, focusing on cutting-edge semiconductor solutions. We work on industry-leading technologies including System LSI, Memory, Foundry, AI/ML, 5G/6G, and Neural processors to deliver world-class products.