RTL Design Engineer

About the Company

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. We co-design the full stack: AI-native EDA systems and advanced ASICs that provide 10-100× more AI inference per dollar and per watt.

Responsibilities

• Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces
• Author functional verification environments using UVM, cocotb, formal property checking, or a combination
• Translate high-level specifications into implementable microarchitectures
• Collaborate with physical design on timing closure, floorplanning constraints, and DFT
• Develop and maintain simulation infrastructure, regression pipelines, and coverage closure flows
• Participate in design reviews and contribute to architecture decisions
• Support tapeout preparation, integration, and post-silicon bring-up

Requirements

• Hands-on experience writing production RTL in SystemVerilog
• Experience closing RTL through synthesis and place-and-route
• Experience authoring verification environments in UVM, cocotb, or formal tools
• At least one successful silicon tapeout in your professional background
• Ability to operate across both design and verification disciplines
• Experience working on datapaths, pipelines, or custom logic
• Strong debugging instincts across simulation, waveforms, and formal counterexamples
• Industry experience in ASIC or SoC design

Preferred Qualifications

• Experience at an AI chip company with tightly coupled design and verification
• Open-source RTL contributions (e.g., Chipyard, OpenTitan, CVA6)
• Familiarity with RISC-V or other open ISAs
• Experience with AI-assisted RTL or EDA tooling
• Exposure to physical design constraints and timing-driven RTL development