R&D Engineer

Responsibilities

• Develop and optimize multi-FPGA partitioning algorithms for the ZeBu emulation compile flow
• Build timing-aware partitioning solutions that incorporate critical path timing criticality into cost models
• Design and enhance a robust partitioning engine to reduce sensitivity to random initial solutions
• Apply analytical partitioning approaches to improve solution quality, stability, and reproducibility
• Work on constraint-aware partitioning for logic/memory resources and inter-FPGA connectivity
• Collaborate with FPGA P&R and runtime teams to validate partitioning decisions and support platform sign-off
• Analyze partitioning bottlenecks and implement scalable C/C++ backend components on Linux

Requirements

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field
• Strong foundation in algorithms, data structures, and graph/hypergraph partitioning
• Experience with C/C++ and performance-oriented software development on Linux/Unix
• Proficiency in scripting languages such as Python or TCL
• Knowledge of optimization techniques and partitioning algorithms (e.g., hMetis, multi-way partitioning)

Preferred Qualifications

• Basic exposure to clock synthesis or multi-cycle path concepts
• Background in analytical approaches to partitioning or large-scale optimization (e.g., spectral or eigenvector-based methods)
• Strong problem-solving, debugging, and experimental evaluation skills

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity, paternity, and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across a wide range of industries.