R&D Engineering Architect

Responsibilities

• Collaborate with R&D teams to develop leading-edge CAD flows for Synopsys IP
• Demonstrate differentiated PPA results on industry standard Synopsys Interface IP protocol designs
• Provide technical support to IP developers, key customers, and test-chip tapeouts in leading-edge nodes
• Deliver scalable CAD flows for multiple Synopsys IP to ensure high quality and performance
• Utilize scripting languages such as Perl and Tcl for automation and optimization tasks
• Stay updated with the latest advancements in ASIC design flow, VLSI, and CAD development

Requirements

• 15+ years of proven experience in ASIC physical design or CAD flows with expertise in complex SoC at advanced process nodes
• Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR-drop/EM analysis, and LVS/DRC
• Proficiency with state-of-the-art CAD tools such as DC, PT, ICC2/FC, ICV, and RedHawk
• Hands-on experience with advanced process technologies like 5nm, 3nm, and 2nm nodes
• Strong proficiency in scripting languages including Perl and Tcl
• Excellent communication, problem-solving, and project management skills

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and annual bonus eligibility

About the Company

Synopsys is a global leader in Electronic Design Automation (EDA), providing the software and tools essential for chip design, verification, and manufacturing. Our engineers enable designers worldwide to extend the frontiers of semiconductors through state-of-the-art technologies like AI/ML and Cloud.