R&D Engineer - AI/ML, HPC

Responsibilities

• Design and implement challenging scientific computing and AI workloads on Cerebras’ Wafer-Scale Engine to advance state-of-the-art performance.
• Lead algorithm–hardware co-design efforts with internal R&D teams and external research partners.
• Build analytical performance models to quantify bottlenecks and guide future chip and compiler design decisions.
• Contribute to the multi-year technology roadmap by identifying high-impact workloads and validating architectural experiments on silicon.
• Publish findings and present research at top-tier conferences such as Supercomputing, SIAM, IEEE, and NeurIPS.

Requirements

• Proficiency in C and Python, with comfort working close to hardware.
• Strong ability to analytically model and optimize the performance of complex systems and algorithms.
• Deep experience in at least one of the following: computer architecture, accelerator design, parallel/high-performance computing, numerical methods, or AI/ML theory.
• Track record of published research or patents in relevant technical venues.
• Excellent communication skills with the ability to present complex material to specialist and cross-functional audiences.

Preferred Qualifications

• PhD in Computer Science, Engineering, Applied Mathematics, Physics, or a related quantitative field.
• Expertise in computational science (e.g., hydrodynamics, molecular dynamics, or PDE-based fields).
• Deep understanding of AI/ML model architecture and optimization methods from first principles.
• Experience in performance engineering, including roofline modeling, bandwidth analysis, and kernel optimization.

About the Company

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, empowering users to run large-scale ML applications with industry-leading training and inference speeds. Our Advanced Technology Group (ATG) serves as our pathfinding organization, exploring new architectures and shaping the technical roadmap for the future of wafer-scale computing.