Principal Verification Engineer

Responsibilities

• Lead end-to-end verification execution for complex Digital IPs and Subsystems to ensure first-pass silicon success
• Evaluate, adopt, and deploy advanced, scalable verification methodologies to manage design complexity
• Own verification quality metrics across planning, execution, and closure phases
• Drive a ‘Zero Defect’ mindset through rigorous process adherence, coverage closure, and defect prevention
• Analyze and improve existing verification flows to enhance efficiency and predictability
• Collaborate with global cross-functional teams including Design, DFT, Architecture, and Validation
• Support pre-silicon and post-silicon validation activities as required

Requirements

• 10–15 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs
• Strong expertise in SystemVerilog and UVM
• Proficiency in C/C++ and solid understanding of HDLs such as Verilog/VHDL
• Experience with industry simulators including VCS, NCSim, ModelSim, or Questa
• Deep expertise in testbench architecture, development, debugging, and verification closure
• Strong knowledge of SVA, functional coverage, and regression management
• Solid understanding of ARM microcontroller architectures and AMBA protocols (AHB, AXI)
• Experience with memory subsystems including SRAM, Flash, DDR, and memory controllers

Preferred Qualifications

• Exposure to formal verification methodologies and tools
• Experience with gate-level simulations and verification planning tools
• Exposure to emulation and pre-silicon validation environments
• Domain knowledge in automotive, graphics/vision accelerators, or high-speed serial interfaces

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a global leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.